"Jitter in Ring Oscillators"

J. McNeill

Ph.D Dissertation, Boston University, Boston, MA (May, 1994)

Abstract

This thesis describes a methodology for analyzing and predicting jitter (phase noise) in ring oscillators. Due to their high operating frequency and ease of integration, use of rings in jitter sensitive applications is becoming more common. One example is in data communication, where a ring is used as the voltage controlled oscillator (VCO) in a phase-locked loop (PLL). Despite the wide use of ring oscillators, their jitter performance has been poorly understood.

The first step in developing this methodology is a technique for relating various measures of jitter in PLLs. The technique establishes correspondence among time and frequency domain measures of jitter with the PLL loop open or closed. Results are given when this time/frequency technique is applied to jitter measurements from an existing PLL. The next step is to determine the fundamental sources of jitter in rings and how they affect the measured performance. A review of analysis techniques for harmonic and relaxation oscillators shows that a different approach is needed to design for low jitter in rings. The approach taken follows naturally from the time/frequency jitter technique developed in the first part of the thesis. A major contribution is the identification of a design figure of merit which is independent of both the ring frequency and number of stages. Experimental results from several rings of different lengths demonstrate that jitter depends primarily on thermal noise sources in the delay stage, and has little to do with the number of stages in the ring.

The final result is a simple design procedure which gives explicit constraints on circuit elements as a function of desired jitter performance. The design of a low jitter ring VCO for a 155MHz clock recovery PLL is described. Some of the inherent limitations of the ring architecture, as well as design techniques for dealing with those limitations, are discussed. Test results are presented for the PLL, which has been fabricated in a dielectrically isolated complementary bipolar process.

Download in PDF format (668K)

Or, a hardcopy of the dissertation can be ordered from University Microfilms International, order number 9422371.

"Jitter in ring oscillators"

J. McNeill

IEEE Journal of Solid-State Circuits, vol. 32, no. 6, pp. 870-879, June, 1997.

Abstract

Jitter in ring oscillators is theoretically described, and predictions are experimentally verified. A design procedure is developed in the context of time domain measures of oscillator jitter in a phase-locked loop (PLL). A major contribution is the identification of a design figure of merit which is independent of the number of stages in the ring. This figure of merit is used to relate fundamental circuit-level noise sources (such as thermal and shot noise) to system-level jitter performance. The procedure is applied to a ring oscillator composed of bipolar differential pair delay stages. The theoretical predictions are tested on 155 and 622 MHz clock-recovery PLL's which have been fabricated in a dielectrically isolated, complementary bipolar process. The measured closed-loop jitter is within 10% of the design procedure prediction.
Index Terms - Design methodology, jitter, noise measurement, oscillator noise, oscillator stability, phase jitter, phase-locked loops, phase noise, voltage controlled oscillators.

Download paper in PDF format (236K)

A Simple Method for Relating Time- and Frequency-Domain Measures of Oscillator Performance

J. McNeill

Invited Paper, 2001 IEEE Southwest Symposium on Mixed Signal Design (SSMSD2001), Austin, TX, February, 2001.

Abstract

This paper presents a simple analysis technique for linking time domain (jitter) and frequency domain (phase noise) measures of oscillator performance. The key concept of the methodology is the definition of a single figure-of-merit in the time- or frequency-domain that relates system-level performance (such as jitter or phase noise) to circuit-level parameters (such as power dissipation and signal amplitude). This methodology is particularly applicable to circuit- and system-level design of voltage-controlled oscillators (VCOs) and phase-locked loops (PLLs). The methodology allows VCO and PLL design and characterization to take place in the domain (time or frequency, PLL open-loop or closed-loop) that provides the most insight into sources of jitter, while allowing a direct link to system-level performance as measured in any other domain. The methodology also speeds simulation since only the open loop VCO need be simulated, which allows a substantial savings in simulation time. Design examples and experimental results are presented for existing PLLs showing good agreement to the theoretical predictions in all jitter and phase noise measurements.

Download paper in PDF format (360K)

Noise in Short Channel MOSFETs

J. McNeill

Invited Paper, 2009 IEEE Custom Integrated Circuits Conference (CICC2009), San Jose, CA, September 2009.

Abstract

For long-channel MOSFETs, the power spectral density of wideband noise in the drain current is predicted by an expression derived from thermal noise in the MOSFET channel. For short channel MOSFETs, observed noise can be much higher than predicted from thermal noise analysis of long channel MOSFETs. While the cause of this excess noise is the subject of some controversy, it can be understood by considering the fundamental difference between shot noise (carrier motions are independent events) and thermal noise (carrier motions are dependent due to thermal equilibration). This paper reviews the literature on noise in short channel MOSFETs and shows that the increased noise can be seen as resulting from the current noise approaching a shot noise limit as carrier transit time in the MOSFET channel becomes so small that thermal equilibration does not have time to occur.

Index Terms - Thermal noise, shot noise, device noise.

Paper | Presentation slides

Transitioning an Engineering Course to Studio Format

J. McNeill and K. Keenaghan

Proceedings of the 2002 Frontiers in Education Conference (FIE '02), Boston, MA, October, 2002

Abstract

The more laboratory-intensive studio format offers the possibility of improving student understanding by providing an interactive, hands-on treatment of the theory as it is taught during lectures. For faculty considering the change in format, one drawback is the significant time investment required in reconfiguring course delivery for the new format. This paper describes the transition to such a studio format, utilizing the results of a test lecture performed prior to the course to better prepare the format to meet the needs of both faculty and students.

Download paper in PDF format (155K)

Download presentation in PDF format (166K)

"Implementation of a charge-based neural Euclidean classifier for a 3-bit flash analog-to-digital converter"

B. Onat, J. McNeill, and U. Cilingiroglu

Proceedings of the IEEE Instrumentation and Measurement Technology Conference (IMTC95), pp. 834-839, April, 1995 [Waltham, MA]

Abstract

This paper describes the implementation of a Euclidean squared classifier with a charge based synaptic matrix and discriminator, based on a previously implemented Hamming classifier. The discriminator circuit is a generalized n-port version of the two-port differential charge-sensing amplifier that is conventionally used in DRAM's for bitline sensing. The analog-to-digital (A/D) implementation was chosen to illustrate the network's classification characteristics, since A/D conversion can be interpreted as classifying an input in terms of A/D quantization levels.

A detailed analysis of the classifier configuration is presented. Design issues are addressed at both the system and circuit levels, and some limitations are identified. Simulation results of the the circuit confirming its theoretical performance are presented, as well as measurements of the implemented chip. The circuit occupies an area of 500x250 um, operates with a single 5V power supply, and consumes less than 1mW of static power.

Download paper in PDF format (808K)

"A CMOS analog integrated circuit for detector readout at a 50MHz pixel rate"

J. McNeill, C. Raanes, and J. Stander

22nd International Congress on High Speed Photography and Photonics, Dennis L. Paisley, Editor, Proc. SPIE vol. 2869 (October, 1996)

Abstract

This paper describes high speed, low noise techniques used in the design of an analog integrated circuit to interface with charge-coupled device (CCD) arrays in CCD camera systems. This IC performs the analog signal processing functions required between the CCD output and analog-to-digital converter (ADC) input. The performance goal is 8-bit linearity and 12-bit channel matching at a pixel rate of 50MHz. Channel gain can be adjusted from 2.7 to 12 in 16 steps as specified by a 4 bit digital word. The chip operates from power supply voltages of +/-5V, dissipates 380 mW / channel, and has an input referred noise of 260uV rms.

Download paper in PDF format (118K)

"Boost Converter Provides Temperature-Controlled Operation of 12V Fan from +5V Supply"

J. McNeill

EDN Magazine Design Idea

Abstract

A temperature controlled pulse-width-modulator (PWM) boost converter allows operation of a 12V brushless DC fan from a +5V supply. The circuit is based on the Unitrode UCC2805, a single chip BiCMOS PWM controller which contains all the necessary circuitry (voltage reference, error amplifier, comparator, MOSFET gate drive, and oscillator) for closed loop PWM power supply control. At maximum boost, a voltage of +10V is provided to the fan, which operates at about 80% of its rated (12V supply) speed. Fan speed is controlled by sensing the ambient temperature in the system enclosure, and reducing the fan supply voltage when maximum cooling is not necessary. Reducing the operating speed of the fan not only saves power but also extends operating life and reduces acoustic noise.

Download paper in PDF format (23K) PostScript format (60K)

"Multi-Probe Impedance Measurement System for Non-Destructive Evaluation and Test of "Green State" Powder Metallurgy Parts"

J. Stander, J. McNeill, and R. Ludwig

1998 IEEE Instrumentation and Technology Measurement Conference (IMTC98)

Abstract

This paper describes an instrument capable of detecting flaws in "green-state" (prior to sintering) powder metallurgy (P/M) parts. The instrument uses a matrix of impedance measurements from a multiprobe array which contacts the surface of the P/M part. The array of measured data is processed to not only detect the presence of flaws, but also determine their location, size, and orientation. Experimental results show detection of flaws ranging in size from 10um to 200um

Download paper in PDF format (87K)

A 50A, 1-us-rise-time, programmable electronic load instrument for measurement of microprocessor power supply transient performance

J. McNeill, M. Lawler, G. Levesque, J. Ruiter, J. Noon

2000 IEEE Instrumentation and Technology Measurement Conference (IMTC2000)

Abstract

Abstract - A prototype instrument has been developed which is capable of providing a transient current of up to 50A with a rise time as low as 1 microsecond. The minimum current, maximum current, and rise time are digitally programmable. This instrument, which simulates the transient current loads drawn by a high-speed microprocessor, allows measurement of the transient performance of switch-mode power supplies designed for use in PC systems. The frequency and duty cycle of the load transient waveform is determined by a digital input signal.

Download paper in PDF format (106K)

"Using the WPI Projects Program to Promote Faculty / Student Research Partnerships"

J. McNeill

Worcester, MA (March 25, 1999)

Abstract

This presentation describes integration of sponsored undergraduate projects and graduate research at the New England Center for Analog and Mixed Signal IC Design.

Download presentation in PDF format (24K) PostScript format (30K)

"NECAMSID: Starting a Center"

J. McNeill

Worcester, MA (April 12, 1999)

Abstract

This presentation describes issues involved in starting a collaborative research center such as the New England Center for Analog and Mixed Signal IC Design (NECAMSID) at WPI.

Download presentation in PDF format (20K) PostScript format (26K)

"Teaching at WPI"

J. McNeill

Worcester, MA (September 10, 1999)

Abstract

Presentation to New Faculty Orientation session.

Download presentation in PDF format (21K) PostScript format (29K)

"Group Therapy: Keeping Your Project Students Moving"

J. McNeill, R. Vaz, S. Vernon-Gerstenfeld

Worcester, MA (November 14, 2005)

Abstract

Are you advising a project that didn't make much progress in A term? Do you wonder how to hold your students accountable and keep them motivated? In this informal, collaborative workshop, the presenters and audience will share and discuss ideas for keeping project students on task. Come with questions and ideas!

Slides

Handouts



"Split-ADC” Digital Background Correction of Open-Loop Residue Amplifier Nonlinearity Errors in a 14b Pipeline ADC"


J. McNeill, S. Goluguri, and A. Nair,

 IEEE 2007 International Symposium on Circuits and Systems (ISCAS2007), New Orleans, May 2007.

Abstract
The "Split ADC" architecture concept is applied to correction of errors due to nonlinearity of an open-loop residue amplifier in a pipeline ADC.  Determination of calibration parameters and correction of errors takes place entirely in the background in the digital domain; no interaction with analog circuitry is required.   An algorithm exhibiting convergence of calibration parameters in fewer than 100 000 conversions is presented.

Paper

Slides