Dr. R. James
Duckworth, AK301, Tel: (508) 831-5204, email: rjduck@wpi.edu
TA: Suganya Subramanian ssubramanian@wpi.edu
Lab help sessions in AK113 Wednesday 3 to 6pm
14 lectures (In AK219, 6.00 pm) starting Wednesday August 30th and ending December 13th
No classes on October 18 (mid-semester break), and November 22 (Thanksgiving)
Project presentations for final project – December 6th
Final exam and final project reports due December 13th .
This is an introductory course on Verilog and
VHDL, two standard hardware description languages (HDLs), for students with no
background or prior experience with HDLs. In this course we will examine some
of the important features of Verilog and VHDL. The course will enable students
to design, simulate, model and synthesize digital designs. The dataflow,
structural, and behavioral modeling techniques will be discussed and related to
how they are used to design combinational and sequential circuits. The use of
test benches to exercise and verify the correctness of hardware models will
also be described.
Course Projects: Course projects will involve
the modeling and synthesis and testing using Xilinx tools. We will be targeting
Xilinx FPGA and CPLDs. Students will need to purchase the NEXSYS3 FPGA
development board for project assignments. (Other synthesis and simulation
tools may be used if these are available to the students at their place of
employment.) Students will have the choice of completing assignments in either
Verilog or VHDL.
Prerequisites: Logic Circuits and
experience with programming in a high-level language (such as C) and a computer
architecture course such as ECE505.
Grading: The final grade is based on the grades for the exam and lab reports. The weight for each part is:
· Final exam - 30%
· initial design project –15% (report and demo signoff due by week 7)
· middle design project – 15% (report and demo signoff due by week 10)
· final design project - 40% (presentation week 13, report and demo signoff due week 14)
· Grade A(90-100), B(80-89), C(70-79)
· No late work accepted
·
Project 1
·
Project 2
·
Final Project
o
ADT7420 Temperature Sensor Data Sheets
o
You must first
register, and then download and install the WebPack
o
(we
just need the Xilinx Vivado Design Suite HL Webpack – logic design edition with SDK. Select SDK during
the Webpack customization installation options.)
o
Manufacturer of
Nexys4DDR Boards
o
http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1338&Prod=NEXYS4DDR
·
Nexys4DDR (Artix 7) Board Tutorials
o
VHDL Decoder Tutorial
– (using Vivado for synthesis and configuring the Nexys4DDR board)
o
MMCM Tutorial MMCM tutorial (verilog)
o
Verilog Decoder Tutorial
(for Basys3)
o
Verilog Counter Tutorial (for
Basys3)
·
Microblaze Resources:
o
Microblaze
Vivado Tutorial to add Microblaze
MCS to project (old ISE version)
o
PG116 Microblaze
Microcontroller Product Guide
o
DS865
Xilinx Product Specification for Microblaze Micro
Controller System
·
Older Material for
Reference
·
Nexys3 (Spartan 6)
Board Tutorials
o
VHDL Decoder Tutorial –
(for Xilinx synthesis and downloading to the Nexys3 board)
o
VHDL
Counter Tutorial – Verilog
Version with Simulation (For Nexys2 board)
o
DCM Tutorial (Verilog)
o
DCM Tutorial (VHDL)
·
Picoblaze Resources:
§
Select the Picoblaze for the Spartan 6 and download the design files
(includes examples)
§
Important: Download
and read the UG129 "Picoblaze 8-bit embedded
microcontroller" document
§
Select the pBlazeIDE and download V3.6 of the assembler/simulator
o
Simple Picoblaze example project files for Nexsys2 Board -
uses LEDs, DIP switches, and UART
§
ece574_pico.vhd is the top level file, ece574.psm is the assembler file,
target is Nexsys2 board.
o
Simple Picoblaze
example project files (Verilog Version) for Nexsys2 Board - uses LEDs, DIP switches, and UART
§
ece574_pico.vhd is the top level file, ece574.psm is the assembler file,
target is Nexsys2 board.
·
VHDL FAQ (http://www.eda.org/comp.lang.vhdl/)
– very useful resource
·
Paper presented at MSE
2005 on Embedded
System Design with FPGAs using HDLs
·
Ten Simple Rules
to follow!
·
Module 3: Combinational Logic
·
Module 4: The Process Statement
·
Module 7: Misc
topics with VHDL
·
Module 8: Test benches with VHDL
·
Module 9: Advanced
Testing with VHDL
·
Module 10: VHDL for Modeling
Verilog Modules
·
Module 1:
Introduction
·
Module
3 & 4: Verilog – Sequential Logic
·
Module 5:
Verilog – Misc topics
·
Module
6: Test benches – Verilog for Testing
·
Module 8:
Verilog for Advanced Testing
·
Metastability, clock domains, pipelines
Academic Honesty:
Although it is OK to discuss
outside of class all homework, laboratory, and exam questions, all work turned
in for homework assignments and examinations is expected to represent
individual solutions to the problems, and laboratory reports are expected to
represent the work of the individual named on the cover page. Having one person
do a homework or lab assignment and another person simply duplicating the
answers or report is considered cheating. Similarly, duplication of materials
such as design, software, flow diagrams, or other documentation between
laboratory teams, from past projects, or other sources is not acceptable. It is
not acceptable to use ANY VHDL or Verilog code from outside sources (including
the Xilinx CORE generator) unless specifically mentioned in the lab
description. All VHDL or Verilog must be your own design. Copying another persons examinations papers, or working from
someone else’s notes, or providing material to another person, or using
material in addition to that allowed during an exam, is considered dishonest as
well. Any acts of academic dishonesty will, at the least, result in immediate
failure of the course for all individuals involved.
Copyright © 2017 R. James Duckworth.
Developed and maintained by R. James Duckworth, rjduck@wpi.edu.