The Effect of Channel Width on Jitter in CMOS Ring Oscillators
Yuping Toh
May, 2002

Abstract

Oscillators are a critical component in many electronic systems and improving their jitter performance is an ongoing process.

Harmonic oscillators offer very good jitter performance but typically require the use of either an off-chip inductor, which will defeat the goal of integration, or the use of an on-chip inductor, which will deliver poorer jitter performance at the cost of die area.

The ring oscillator is easy-to-design and easily integrated. Without the need for inductors, the ring oscillator occupies far less die area than a harmonic oscillator. Unfortunately, the jitter performance of the ring oscillator falls short of the jitter performance of harmonic oscillators.

Despite its shortcomings the ring oscillator satisfies a niche where moderate jitter performance, high levels of integration with low die real estate, and a wide tuning range are required.

This thesis investigates the relationship between MOSFET channel width and the jitter in ring oscillators with the goal of finding out if wider devices will produce lower jitter. A test chip with four VCOs was realized in silicon on a TSMC 0.35um CMOS process.

The results indicate that increasing transistor width improves jitter in a manner consistent with the theoretical predictions.

Thesis (PDF format, 3.5MB)

Design of Low Noise, Low Power Linear CMOS Image Sensors
Pavan Kumar Hanumolu
April, 2001

Abstract

The implementation of active pixel based image sensors in CMOS technology is becoming increasingly important for producing imaging systems that can be manufactured with low cost, low power, simple interface, and with good image quality. The major obstacle in the design of CMOS imagers is Fixed Pattern Noise (FPN) and Signal-to-Noise-Ratio (SNR) of the video output. This research focuses on minimizing FPN and improving SNR in linear CMOS image sensors which are needed in scanning and swiping applications such as finger print sensing, spectroscopy, and medical imaging systems. FPN is reduced in this research through the use of closed loop operational amplifiers in active pixels and through performing Correlated Double Sampling (CDS). SNR is improved by increasing the pixel saturation voltage.

This thesis concludes that FPN can be reduced using the closed loop opamp buffers. The major FPN noise sources are the shot noise from the photodiode, kTC noise from the sampling capacitors, and offset mismatches in the sample and hold amplifiers all of which are not compensated by CDS. Sample and hold amplifier offset mismatch is identified as the largest contributor to FPN.

The digital interface issues of CMOS imagers are also studied. The design of a 12-bit pipelined analog-to-digital-converter (ADC) in standard CMOS technology is presented. The integration of this ADC onto the imager chip would result in a digital image sensor.

Thesis (PDF format, 1.3MB)

Thesis defense presentation (PDF format, 2.4MB)