Author: Brigitte Servatius and Herman Servatius
Reference: Obzornik za Matematico in Fiziko, Vol.50, No.1, Jan. 2003, 14--20.
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Abstract: A dual-eulerian graph is a plane graph which has an ordering defined on its edge set which forms simultaneously an Euler circuit in the graph and an euler circuit in the dual graph. Dual-eulerian graphs were defined and studied in the context of silicon optimization of cmos layouts. In this paper we examine the connections between the dual eulerian property, Petrie walks, and the connectivity of the graph. We will also consider the dual-eulerian property for graphs embedding in surfaces of higher genus.