PROJECT SUMMARY

Research plan summary

A critical component in any integrated communication system is an oscillator that provides a time/frequency reference for the data transmission and detection process. There are three main classes of oscillators that can be considered for integrated circuit design: harmonic, multivibrator, and ring oscillators. The harmonic and multivibrator oscillators have been thoroughly analyzed and procedures have long been available for designing to a given noise specification. The broad class of ring oscillators offer many advantages for integrated oscillator design, but until recently there were no procedures available to design for a desired level of noise performance.

The research that is described in this proposal is based on a new design methodology for ring oscillators that has been proven successful at frequencies up to 155MHz in a bipolar IC process. The key insight from this methodology is the linkage of system-level performance to fundamental limits imposed by circuit-level considerations, for example thermal and shot noise. The value of this research in targeted, specific applications has been shown by industry: Analog Devices Semiconductor, Inc., has already committed to fund a fellowship for graduate student time to extend this methodology to the speed of 622MHz required for the next generation of information transmission systems. The purpose of the research proposed to NSF is to extend and broaden the methodology to higher speeds, new applications, and more fabrication technologies. The low jitter oscillator design techniques will be extended in several ways:

• Higher speed: 2.5 GHz oscillator design
• Fabrication technology: CMOS
• Reduced supply voltage: 3.3V and below
• Other applications: wireless communication, high speed microprocessor design, oversampled data conversion.

Teaching plan summary

• Graduate: by direct involvement in research, and development of a graduate course which addresses fundamental noise issues in the context of mixed signal circuits and systems.
• Undergraduate: by involvement in senior-year research projects which will benefit students bound for either industry or graduate school.
• Secondary: by outreach to younger students from groups traditionally underrepresented in science, through participation in research internships and awareness of the field of electrical engineering.

Research Plan: LOW-NOISE DESIGN TECHNIQUES FOR TELECOMMUNICATIONS

INTRODUCTION

Section (iii) describes a relatively straightforward extension of the design methodology from 155MHz to 622MHz. This is a short-term project which is closely coupled to a particular data communication application. Preliminary work on this project has shown that, although the basic approach of the methodology is sound, some of the simplifying assumptions that hold at 155MHz are being stretched at 622MHz. To maintain confidence in the design methodology, further improvements in system performance must be accompanied by improvements in the design methodology. Section (iv) describes the necessary improvements in the design methodology. This is a long term project and is more research oriented, since it is not as closely coupled to a particular application. As will be seen, improvements in each of the areas of speed, power consumption, and process technology stress different aspects of the simple design methodology. It is expected that expanding the methodology in each of these areas will yield valuable insights for the design of low noise integrated systems.

i) ORIGINAL APPLICATION

For this application, the measurement goal is to determine how well the clock recovery function can be performed. The timing diagram in Figure 1 shows the ideal case when clock recovery is performed perfectly: There is no phase error in the recovered clock, and RCLK samples Vin at the exact center of the bit period. This gives the minimum bit error rate (BER). Any deviation of RCLK from the ideal will increase BER.

Increased BER is not the only negative effect of jitter in serial data communication systems. In a repeatered system, where the recovered clock is also used as a transmit clock for a subsequent data link, phase jitter reduces the number of links that can be cascaded before jitter becomes unacceptably large [2].

In evaluating the performance of a data link, the end user must be concerned with many other possible influences on BER. Among other factors that can degrade system BER in a fiberoptic link are power loss and dispersion in the optical fiber, inadequate optical power input at the transmit end, and noisy optical-to-electronic conversion at the receive end.

To assess its contribution to BER, the clock recovery block can be tested independently, as shown in Figure 2 . The input is an ideal data waveform; the recovered clock is then compared to the transmit clock using a communications signal analyzer. If there were no jitter, the phase difference between the clocks would be constant (due only to static phase and propagation delay differences). In the presence of jitter, there is a distribution of phase differences. To estimate the distribution, the CSA compiles a histogram of phase measurements as shown in Figure 2. The standard deviation of this distribution is the end user's figure-of-merit for characterizing the jitter performance of the clock recovery block. Jitter errors are typically of order 1% of a unit interval; at a 155MHz data rate the unit interval is 6.4 nsec, so the jitter errors to be measured are of order picoseconds. Of course the time base stability of the measuring instrument must be better than the clock waveform that is being measured.

There are additional ways of measuring phase and phase errors. The phase noise power spectral density is a measure of stability in the frequency domain. In this case a spectrum analyzer or specialized phase noise measurement system is required. In properly functioning systems, the magnitudes of the phase noise measurements is quite small; typically of order -100dBc/Hz or lower.

One approach for generating the recovered clock is to use a phase-locked loop (PLL) [3-7] as shown in Figure 3 . This has the advantage of being integrable, and thus relatively inexpensive. In the PLL, the time reference for the recovered clock is provided by a voltage controlled oscillator (VCO). The design methodology described in section (ii) was developed to connect fundamental, circuit-level noise sources to the system level instability of the VCO clock.

In addition to this work's relevance to serial data transmission systems, there are several other important system applications requiring low jitter performance from PLLs that perform a clock recovery function:

Disk drive clock recovery

Data is usually stored on magnetic media with no reference track to indicate bit boundaries. Therefore when data is read from the magnetic medium, there is a need to recover a clock signal from the data to determine the bit boundaries. Low jitter is necessary since any increase in jitter increases read errors [8].

Generating high speed digital clocks on-chip

As digital processor and memory chips become capable of operating at clock rates exceeding 100 MHz, the problem of distributing such a high speed clock throughout a system becomes more difficult. One approach to solving this problem is to distribute a lower frequency clock, and multiply this clock to the higher frequency with an on-chip PLL [9]. Low jitter is necessary since any increase in jitter reduces timing margin for digital signals that rely on the clock.

Oversampled Data Conversion

A PLL can be used to generate the high-speed clock required for delta-sigma A/D and D/A conversion in digital audio applications. Low jitter is necessary since phase noise on the clock can be aliased into the audio band to produce audible, objectionable artifacts in the reconstructed analog waveform [10].

Wireless Communication

A PLL can be used to integrate the local oscillator (LO) function required for signal modulation and demodulation in radio frequency (RF) communication ICs. In this case, frequency-domain performance is important since phase noise on the LO will translate into noise in the signal band after demodulation [11].

ii) THEORETICAL APPROACH

A relaxation (multivibrator) oscillator is characterized by an equivalence to one energy storage element, with additional circuitry that senses the element state and controls its excitation to give a periodic output signal [17]. Fully integrated clock recovery PLLs have been described using multivibrator VCOs [6, 18-20]. In general, jitter analysis for this type of oscillator has been approached in the time domain [17, 21, 22]. The jitter performance of the multivibrator is known to be worse than the harmonic oscillator, although design techniques for improving jitter have been available since the early 1980s [17, 23, 24]. For fully integrated VCOs, there is a need for improvement of jitter beyond the best achieved by the multivibrator.

The third class of oscillator is the ring oscillator: a loop of N delay stages with a wire inversion, as shown in Fig. 3. The ring will oscillate with a period of 2N times the stage delay. Voltage controlled ring oscillators have frequently been explored as an alternative to the multivibrator for fully integrated, lower jitter clock recovery PLLs [3, 25-31]. Like the multivibrator, a ring oscillator is fully integrable. In addition, some of the empirical results show promise of excellent jitter performance [31]. However, prior to the development of the methodology described here, a survey of the literature showed that there had been no theoretical analysis of jitter in ring oscillators. Thus there were no techniques available for designing to achieve lower jitter in a ring oscillator. Perhaps one reason that analysis of jitter in ring oscillators has lagged is that the ring does not fit well into either of the harmonic or multivibrator oscillator models. The number of energy storage elements is not as explicit; in fact there are many "energy storage elements" since the ring is composed of multiple stages. Thus, a new approach was needed to give designers confidence in designing to achieve a given level of jitter performance.

The design methodology that fulfills this goal was developed by the author and verified in [4]. First a simple technique was developed to establish correspondence among time and frequency domain measures of jitter with the PLL loop open or closed. Relating time and frequency measures is important to ensure that the design methodology is relevant to all of the applications mentioned in section (i) above, since the effects of noise in limiting performance can be viewed in the time or frequency domain. Relating open-loop and closed-loop performance is important to simplify the design process, since an open-loop oscillator can be examined (and simulated) in isolation from other system components.

The key challenge that was addressed in developing the design methodology is connecting noise performance at four different levels of complexity, as shown in Figure 3: the overall clock- and data-recovery system, the phase-locked-loop within the clock recovery function, the delay stages in the PLL voltage controlled ring oscillator, and the individual circuit-level components within the delay stage. The major contribution of this approach is the identification of a time domain figure-of-merit that applies across all levels of complexity. At the system level, this figure- of-merit can be related to jitter performance as measured by the end-user in both the time and frequency domains. At the component level, the figure-of-merit is related to fundamental sources of jitter in the oscillator, such as thermal noise and shot noise. The result is a design procedure which gives explicit constraints on circuit elements (such as resistance and capacitance values and bias currents) as a function of desired jitter performance.

To keep the scope of the analysis manageable, the technique was developed in the context of a ring oscillator composed of differential-pair delay stages fabricated in a bipolar technology. To simplify the analysis and make the results easier to interpret, a number of assumptions were made:

1. The delay of the differential pair is dominated by a single RC time constant
2. There is no gate-to-gate interaction of jitter errors
3. To first order, jitter is independent of the number of delay stages in the ring
4. The oscillator signal is much larger than the linear region of the differential pair
5. The magnitude of the oscillator signal is much larger than the magnitude of the noise that causes the jitter

With these assumptions, the resulting design equations yielded significant intuitive insight into the effects of design choices on system-level noise performance. For example, it was discovered that there are straightforward, fundamental linkages between system level noise and circuit level considerations such as power dissipation and oscillator waveform amplitude. Additional confirmation of the validity of this approach was obtained by expressing the well known results of the harmonic and multivibrator design procedures in the form of this design methodology. The resulting expressions for the relationship between noise performance and fundamental power dissipation were similar for all three classes of oscillators. This is a strong indicator that this approach has promise to apply to the entire class of ring oscillators. The key question to be answered is: What will happen as assumptions 1 - 5 need to be modified or discarded as the methodology is extended?

UNIQUE FEATURES OF THIS APPROACH

Successful theoretical description of a widely used class of oscillators

Until this approach was developed, there were no ring oscillator design techniques comparable to those available for harmonic and multivibrator oscillators. Extension of this approach will further enable confident design of high performance integrated oscillators for a wide variety of important applications.

Relating noise performance over several levels of complexity

These techniques allow the designer to conduct analysis and synthesis at whichever level of complexity is most convenient, while confidently being able to predict the ultimate system-level jitter. For example, a full (transient analysis mode) simulation of the VCO would require an inordinate amount of computer time due to the large number of components in the VCO circuit. However, simulation at the gate level is tractable and provides valuable information which can be related to system-level jitter performance.

Speed design by relating fundamental parameters to system level performance

The ability to traverse several levels of complexity, from system-level performance to circuit- level constraints, is very valuable in the early stages of design when system level power and performance budgets are being roughed out. For example, in the case of low power design, the technique sets a limit on the best possible jitter that can be achieved for a given DC power dissipation. Thus, even before proceeding with detailed circuit design, the designer knows whether a given jitter performance goal can be achieved within a given power constraint. As another example, the technique relates waveform amplitude and jitter. Thus in the case of low supply voltage design (with little headroom for large signal swings), it is possible to immediately determine the best possible jitter that can be achieved at a given signal amplitude.

Identification of individual contributions to jitter performance

The design procedure yields expressions for the absolute noise contributions from different sources of jitter, allowing the designer to determine which source is the major contributor in a given design. This is an essential part of simplifying the design process, which at the circuit level involves many variables, for example transistor geometry, resistance and capacitance values, and DC bias currents. Considering all the permutations of design decisions, there are literally hundreds of design options available. The ability to identify which options are most effective in reducing noise is tremendously valuable in speeding design.

Relating open loop and closed loop performance and measurements

The relationship between open-loop and closed-loop performance simplifies design by allowing the designer to isolate VCO design as a separate task. In addition, the open-loop/closed- loop relation is also useful in evaluation of actual devices. From open loop VCO measurements, we can predict what the closed loop performance should be if limited only by the VCO jitter. Then we can compare this prediction with actual measurements to determine if other PLL components (such as the phase detector or loop filter) are degrading the closed loop performance.

iii) 622MHz SYNTHESIZER FOR TELECOMMUNICATIONS

This work will begin to investigate the applicability of the jitter theory at higher speeds. As mentioned previously, the design procedure has been used to design low-jitter VCOs in the 155MHz frequency range. The noise predictions of the theory have been quite good, within 10% of actual measurements. Some preliminary investigation at 622 MHz indicates that there will be some accuracy degradation as the simplifying assumptions begin to break down. How much accuracy degradation will there be at higher speeds, where some of the simplifying assumptions made in the theory may not apply? If there are high speed effects, can the theory be modified to take them into account?

As part of the fellowship support, Analog Devices has committed to provide some support in the area of test equipment - specifically, some time will be made available on a bit error rate (BER) tester to test performance in the particular data communication application. Although this is sufficient for Analog Devices' product development purposes, it is insufficient to verify the theoretical predictions in the frequency domain and across different levels of complexity. Due to the time and money constraints of the industry environment, there is no time available on general purpose test equipment to investigate the full implications of the design methodology.

It is essential to verify the methodology by fabricating and fully testing prototype chips that implement a system function. As indicated above, Analog Devices is supporting fabrication. However, since only "pass-fail" testing is being supported under the Analog Devices fellowship, NSF support is being requested for test equipment under the CISE Research Instrumentation Grant program. This will allow full testing of fabricated chips, and comparison of the measured performance to the predictions of the design methodology. This equipment will also be used in evaluating the integrated circuits designed and fabricated under the long-term research described below.

iv) METHODOLOGY EXTENSIONS: LOW NOISE INTEGRATED CIRCUIT DESIGN FOR TELECOMMUNICATION SYSTEMS

The goal is to extend the low jitter oscillator design methodology in several ways:

Higher Speed: 2.5 GHz oscillator design

As stated earlier, investigation into 622MHz operation is a short term goal that will be partially supported by Analog Devices. The next SONET data transmission rate is 2.5GHz, which is a natural goal for the next stage of investigation. This is a suitable frequency for other reasons as well - a capability to 2.5GHz incorporates wireless communications such as cellular telephony at frequencies in the 800MHz to 1.9GHz range [11].
There are two ways to modify the ring oscillator design to allow operation at these higher frequencies: reduce the delay time of each gate, and reduce the number of gates in the ring. These steps inherently cause the simplifying assumptions to break down:

• Assumption 1: As the dominant RC time constant is reduced to reduce delay and increase operating frequency, other delay mechanism such as carrier transit time and parasitic capacitances become significant contributors to delay. Representing the gate delay as being due to a single RC time constant is no longer feasible, and the theory will have to be broadened to take into account the effects of other significant delay mechanisms.
• Assumption 2: As shorter ring lengths are used to achieve higher frequency operation, gate- to-gate interaction of jitter errors becomes more likely. The theory will have to be broadened to consider the effects of previous jitter errors on the jitter errors of succeeding delay stages.
• Assumption 3: If there is gate-to-gate interaction, it is reasonable to expect that jitter will no longer be independent of the number of delay stages in the ring. The theory will need to be extended to incorporate the effects of rings of different lengths.

Will it be possible to express the results of this broadened theory in a simple enough fashion to preserve the intuition and insight offered by the simple theory? This is the major question to be addressed as the methodology is extended to higher speeds.

Fabrication technology: CMOS

The original application for the simple theory was in a bipolar IC process. However the majority of ICs are fabricated in CMOS for cost reasons, even though the lower transconductance of MOS transistors make the CMOS process less technically suitable for analog tasks such as oscillator design. For the design methodology to be applicable to as many designs as possible, it is very important that it be extended to include CMOS. Development of the original theory was considerably simplified by assuming the oscillator signal to be much larger than the linear region of the differential pair (assumption 4). This "large signal" assumption is no longer true in the CMOS process, and the theory will need to be modified to take this into account.

Low Power / Low supply voltage

The increasing emphasis on portable personal computing and communication [11] has intensified the drive to lower power, lower voltage integrated circuits. The simple theory was developed in a 5V-power-supply environment, where it was easy to meet the "large signal" assumption described above. As supply voltages shrink to 3.3V and below, however, there is less "headroom" for a large signal swing. As the oscillator signal amplitude is necessarily reduced, the "large signal" assumption breaks down.

Other applications

The overall applicability of the theory has been demonstrated in the system-level application of data communication, in which the fundamental performance metric is a time-domain measure. Other applications, such as wireless communication and oversampled data conversion, have performance metrics in the frequency domain. To expand the proven fields of applicability of this theory, it will be necessary to fabricate ICs that perform system level functions in these fields. Then the ability of the theory to link performance across several levels of complexity can be verified in these other important application areas.

METHOD

The goal of the special purpose evaluation ICs is to (as nearly as possible) isolate the assumptions of the basic theory to test where they break down, and illuminate how the theory needs to be modified and extended to capture circuit and system noise behavior at higher oscillator frequencies. The original methodology works at very well at low frequencies such as 155MHz where the simplifying assumptions hold. The simplifying assumptions trade off accuracy, but at low speeds the accuracy loss is modest and the bonus is a simple theory with intuitively pleasing results that provide a powerful guide to design. Pushing to the higher frequencies required by future applications (2.5GHz) inherently breaks these assumptions, and we can expect that significant modifications of the theory will be required.

The ICs that implement a system-level function are needed since the essential feature of the methodology is linking circuit level considerations to system-level performance. As the theory is modified, it is essential to verify the resulting design procedure by fabricating and testing prototype chips that implement a system function.

Research impact

Teaching Plan

As can be seen from my biographical sketch , from 1983 to 1990 I worked in industry as a practicing engineer, both as a designer and as a manager of design groups. This experience has indelibly formed my outlook on teaching. My goal is an education that produces a design engineer who is knowledgeable in all stages of the design process including manufacturing, testing, and the end customer's application. Note that this is indeed education, rather than training: the design methodology described above is not a mindless "cookie cutter" procedure, but rather forces the designer to confront fundamental physical issues. Being aware of fundamental considerations is essential to fundamental advances in circuit performance.

I have already received some funding from industry partners (Analog Devices, EG&G Reticon) to conduct applied research. Using this funding, I have been able to set up a lab facility with workstations and software for the complete circuit design and simulation process required for success in a production environment: schematic capture, simulation, layout, parasitic extraction, layout-vs.-schematic verification. Fabrication facilities are available through MOSIS and the industry partners. The equipment required to test the fabricated circuits (thereby verifying the design principles and completing the design process) has been purchased under the CISE Research Instrumentation Grant program. The lab will be a tremendous enabling resource for test and evaluation to "complete the loop" for the design process. By pushing for a capability to include 2.5GHz speeds, this lab will be a valuable resource for many years to come.

Involving undergraduate students in research

A graduation requirement for WPI seniors is completion of the Major Qualifying Project (MQP), a capstone design experience in the student's major field. I have completed a revamping of the undergraduate analog curriculum so that students entering the senior year will be able to complete a mixed signal integrated circuit design as their MQP project. The students will have full access to this lab to work on the design and test of their integrated circuit project. An example of this commitment is an MQP that I am now advising, in which a three-student team is designing an integrated circuit for a hand-held pH meter. This project is in collaboration with researchers in WPI's Biomedical Engineering department and the University of Massachusetts Medical School in Worcester. The IC will allow speedy measurement of tissue acidity, which has been determined to be an indicator of infection. The IC will interface to the pH probe at the input, perform all necessary signal processing and data conversion, and interface to an LCD readout to display the pH measurement.

Interdisciplinary collaboration

Graduate recruitment

Graduate teaching plan

This course will focus on the application of stochastic process analysis techniques to problems encountered in analog and mixed signal integrated circuit design. The course is intended for first year graduate students and seniors. The course will begin with a demonstration of fundamental concepts through design, experiment, and simulation, and culminate in a design project showing that the students have mastered the ability to apply probabilistic concepts in a mixed signal integrated circuit design.

In addition to the significance of this course as an addition to the graduate curriculum, I believe that this would also be valuable to engineers in the field who would be able to take this course on a part-time or non-degree basis. It has been my experience that engineers in industry, under tremendous cost and schedule pressure, don't really understand noise and just get by on "rules of thumb." This is fine until the engineer encounters a situation where the rule of thumb fails - without a theoretical context to describe and analyze the problem, the engineer is at a dead end. This course would satisfy what I believe is a hunger on the part of practicing engineers to bridge theory and practice in understanding noise and random processes in real world circuits and systems.

My experience with my Ph.D. thesis represents a prior accomplishment in this area. I gave several in-house presentations at Analog Devices, Inc., who funded my Ph.D. research. In every case there was tremendous interest, since the theoretical technique developed in the thesis was demonstrated to predict the noise performance of a 155MHz oscillator to within 10% of the design value.

Teaching experience

• The instructor established clear objectives for the course
• The instructor organized the course well
• The instructor was well prepared to teach each class
• The instructor stimulated my interest in the subject matter
• The instructor provided adequate assistance outside the classroom

The evaluation results for the six courses I have taught since coming to WPI are shown in Table 1. "N" indicates the number of student responses in each case. In courses ranging from the sophomore level (course numbers 2201, 2012) through senior (4902) and first year graduate (529), an average of 98% of the students agree or strongly agree with a positive evaluation of my teaching ability. I believe this demonstrates my commitment to excellence in teaching, and indicates that I am able to transfer the insights and experiences of research into the classroom.

Table 1. Course Evaluation Results.

COURSE	TITLE	SD %	D %	A %	SA %	N
2201	Microelectronics I	0	3	47	50	64
2012	Introduction to Digital Circuits	0	1	41	57	45
3204	Microelectronics II	1	2	36	60	28
3204	Microelectronics II	0	2	38	60	31
4902	Bipolar Analog IC Design	0	0	36	64	8
529	CMOS Analog IC Design	0	1	48	50	17
TOTAL		0.2	1.9	41.1	56.8	193

Outreach to secondary-school students: the STRIVE program

During the summer of 1995, I worked with two Strive students, who worked a two-week internship in my laboratory. This work was an example of the linkage I try to maintain between my research and education - the students worked on circuitry for a 20 bit analog-to-digital converter for use in a collaborative project with the M.I.T. Center for Space Research. The students built a prototype, tested its performance, and presented their results at a departmental research seminar.

Outreach to pre-secondary students: The Charles Houston Project

A representative of the project approached the ECE department in early 1995 about contributing to this program, and I volunteered to coordinate our participation. The result was a three-hour session in which the student activities included:

• demonstrations of principles in electrostatics, magnetics, and electronics
• constructing simple circuits
• building an AM radio
• faculty members discussing careers in electrical and computer engineering.

SUMMARY

REFERENCES

1. ---, "Synchronous optical network (SONET) transport systems - common generic criteria," Bellcore Technical Advisory, vol. TA-NWT-000253, Issue 6, Sept. 1990.
2. Trischitta, P. R., and P. Sannuti, "The jitter tolerance of fiber optic regenerators," IEEE Transactions on Communications, vol. COM-35, no. 12, pp. 1303-1308, Dec. 1987.
3. J. A. McNeill, R. Croughwell, L. DeVito, and A. Gusinov, "A 150 mW, 155 MHz phase locked loop with low jitter VCO," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), vol. 3, pp. 49-52, May, 1994 [London, U.K.]
4. J. McNeill, "Jitter in ring oscillators," Ph.D. dissertation, Boston University, 1994.
5. Buchwald, A. W., K. W. Martin, A. K. Oki, and K. W. Kobayashi, "A 6-GHz integrated phase-locked loop using AlGaAs/GaAs heterojunction bipolar transistors," IEEE Journal of Solid-State Circuits, vol. SC-27, no. 12, pp. 1752- 1762, Dec. 1992.
6. DeVito, L., J. Newton, R. Croughwell, J. Bulzacchelli, and F. Benkley, "A 52MHz and 155MHz clock-recovery PLL," ISSCC Digest of Technical Papers, pp. 142-143, 1991.
7. Nava, M. D., J. Bulone, D. Belot, and L. Dugoujon, "A 622 Mb/s line terminator for the ATM network," ISSCC Digest of Technical Papers, pp. 104-105, February, 1993.
8. Negahban, M., R. Behrasi, G. Tsang, H Abouhossein, and G. Bouchaya, "A two-chip CMOS read channel for hard-disk drives," ISSCC Digest of Technical Papers, pp. 216-217, February, 1993.
9. Horowitz, M., A. Chan, J. Cobrunson, J. Gasbarro, T. Lee, W. Leung, W. Richardson, T. Thrush, and Y. Fujii, "PLL design for a 500Mb/s interface," ISSCC Digest of Technical Papers, pp. 160-161, February, 1993.
10. Harris, S., "The effects of sampling clock jitter on Nyquist sampling analog-to-digital converters, and on oversampling delta-sigma ADCs," Journal of the Audio Engineering Society, vol. 38, pp. 537-542, July, 1990.
11. H. Sato, K. Kashiwagi, K. Niwano, T. Iga, T. Ikeda, and K. Mashiko, "A 1.9GHz single-chip IF transceiver for digital cordless phones," ISSCC Digest of Technical Papers, pp. 342- 343, February, 1996.
12. H. Ransijn and P. O'Connor, "A PLL-based 2.5 Gb/s GaAs clock and data regenerator IC," IEEE Journal of Solid-State Circuits, vol. SC-26, no. 5, pp. 1345-1353, Oct. 1991.
13. N. M. Nguyen and R. G. Meyer, "A 1.8 GHz monolithic LC voltage-controlled oscillator," ISSCC Digest of Technical Papers, pp. 158-159, 1992.
14. W. A. Edson, "Noise in oscillators," Proceedings of the IRE, pp. 1454-1466, Aug., 1960.
15. M. J. E. Golay, "Monochromaticity and noise in a regenerative electrical oscillator," Proceedings of the IRE, pp. 1473-1477, Aug., 1960.
16. D. B. Leeson, "A simple model of feedback oscillator noise spectrum," Proceedings of the IEEE, vol. 54, pp. 329-330, 1966.
17. C. J. M. Verhoeven, "First order oscillators," Ph. D. Thesis: Delft University, 1990.
18. K. Kato, T. Sase, H. Sato, I. Ikushima, and S. Kojima, "A Low-Power 128-MHz VCO for Monolithic PLL IC's," IEEE Journal of Solid-State Circuits, vol. SC-23, no. 2, pp. 474-479, April, 1988.
19. A. Sempel, "A fully integrated HIFI PLL FM demodulator," ISSCC Digest of Technical Papers, pp. 102-103, February, 1990.
20. M. Souyer and H. A. Ainspan, "A monolithic 2.3Gb/s 100mW clock and data recovery circuit," ISSCC Digest of Technical Papers, pp. 158-159, February, 1993.
21. A. A. Abidi and R. G. Meyer, "Noise in relaxation oscillators," IEEE Journal of Solid-State Circuits, vol. SC-18, no. 6, pp. 794-802, Dec. 1983.
22. B. W. Stuck, "Switching-time jitter statistics for bipolar transistor threshold-crossing detectors," M. S. thesis, Massachusetts Institute of Technology, 1969.
23. J. G. Sneep and C. J. M. Verhoeven, "A New Low-Noise 100-MHz Balanced Relaxation Oscillator," IEEE Journal of Solid-State Circuits, vol. SC-25, no. 3, pp. 692-698, Jun., 1990.
24. C. J. M. Verhoeven, "A high-frequency electronically tunable quadrature oscillator," IEEE Journal of Solid-State Circuits, vol. SC-27, no. 7, pp. 1097-1100, July, 1992.
25. M. Banu and A. Dunlop, "A 660Mb/s CMOS clock recovery circuit with instantaneous locking for NRZ data and burst- mode transmission," ISSCC Digest of Technical Papers, pp. 102-103, Feb., 1993.
26. M. Banu, "MOS Oscillators with Multi-Decade Tuning Range and Gigahertz Maximum Speed," IEEE Journal of Solid-State Circuits, vol. SC-23, no. 6, pp. 1386-1393, Dec. 1988.
27. S. K. Enam and A. A. Abidi, "A 300MHz CMOS voltage- controlled ring oscillator," IEEE Journal of Solid-State Circuits, vol. SC-25, no. 1, pp. 312-315, Feb., 1990.
28. T. H. Hu and P. R. Gray, "A monolithic 480Mb/s parallel AGC/decision/clock recovery circuit in 1.2µm CMOS," ISSCC Digest of Technical Papers, pp. 98-99, February, 1993.
29. J. Scott, R. Starke, R. Ramachandran, D. Pietruszynski, S. Bell, K. McClellan, and K. Thompson, "A 16MB/s data detector and timing recovery circuit for token ring LAN," ISSCC Digest of Technical Papers, pp. 150-151, February, 1989.
30. K. M. Ware, H.-S. Lee, and C. G. Sodini, "A 200MHz CMOS phase-locked loop with dual phase detectors," ISSCC Digest of Technical Papers, pp. 192-193, February, 1989.
31. B. Lai and R. C. Walker, "A monolithic 622Mb/s clock extraction data retiming circuit," ISSCC Digest of Technical Papers, pp. 144-145, Feb., 1991.
32. J. Stander, J. Plunkett, R. Ludwig, J. McNeill, D. Zenger, "Nondestructive evaluation method for 'green-state' powder metal parts," Proceedings of the 15th Review of Progress in Quantitative Nondestructive Evaluation, D. O. Thompson and D. E. Chimenti, editors, August, 1996.

For More Information...