ECE3829: Advanced Digital System Design with FPGAs

A Term 2017

Test 3 Solutions


Test 3 Preparation – complete by Tuesday Solutions


This is a new course replacing ECE3810. It is recommended for anyone who has taken ECE2029 and ECE2049.



You will need the Digilent BASYS3 development board (you should have this already from ECE2029) to be able to complete the lab assignments. You can buy this board for $89 (academic pricing) directly from Digilent:

or from the WPI bookstore.


If you want to work at home on the lab projects (recommended) than you will need to install the Xilinx Vivado Design Suite HL Webpack edition on your own PC (note the OS and system requirements). We just need the logic design version with SDK (select SDK during the Webpack customization installation options).


We will use the Basys3 board and Xilinx software throughout the course for the four lab assignments.



Dr. R. James Duckworth, AK301, Tel: (508) 831-5204, email:

Office hours: MTRF 10 to 11am (send email for other times)


Graduate Tutors: Suganya Subramanian, Kewal Vora

Senior Tutors: Duong Nguyen, Ben Titus

Help/Lab sessions: Sunday 3 to 6pm (in AK113) tbd

Lectures, Labs.      

25 lectures (in AK233) including three exams

Lab sessions: (in AK113) Tuesday 8 to 10.50, 2 to 4.50, and Thursday 2 to 4.50

Note: You only need to go to lab sessions to get help or to have your projects signed off.

Course Description

This course covers the systematic design of advanced digital systems using FPGAs. The emphasis is on top-down design starting with high level models using a hardware description language (such as VHDL or Verilog) as a tool for the design, synthesis, modeling, test bench development, and testing and verification of complete digital systems. These types of systems include the use of embedded soft core processors as well as lower level modules created from custom logic or imported IP blocks. Interfaces will be developed to access devices external to the FPGA such as memory or peripheral communication devices. The integration of tools and design methodologies will be addressed through a discussion of system on a chip (SOC) integration, methodologies, design for performance, and design for test.

Topics: 1. hardware description languages, system modeling, synthesis, simulation and testing of digital circuits; 2. design integration to achieve specific system design goals including architecture, planning and integration, and testing; 3 use of soft core and IP modules to meet specific architecture and design goals.

Laboratory exercises:  Students will design and implement a complete sophisticated embedded digital system on an FPGA. HDL design of digital systems including lower level components and integration of higher level IP cores, simulating the design with test benches, and synthesizing and implementing these designs with FPGA development boards including interfacing to external devices.

Recommended background: ECE2029 and ECE 2049

Notes:  Students may not receive credit for ECE3829 if they have received credit for ECE 3810.

Textbook: (Not required but recommended) FPGA Prototyping using Verilog Examples – Xilinx Spartan-3 Version, by Pong P. Chu, Wiley (ISBN: 978-0-470-18532-2)

An inexpensive ($19.95) reference book is Verilog by Example – A Concise Introduction for FPGA Design, by Readler (ISBN 978-0-9834973-0-1)

A good book focusing on VHDL is RTL Hardware Design using VHDL – Coding for Efficiency, Portability, and Scalability” by Pong P. Chu, Wiley.

A book focusing on embedded systems is Embedded Systems Design with Platform FPGAs: Principles and Practices by Sass and Schmidt, Morgan Kaufman

Help Sessions: See TA and Senior Tutor help session above

Homework: There is no formal homework for the course but make sure you try lots of design examples and read the reference materials and data sheets.

Lab Assignments: There will be four labs. Lab signoff and reports are expected by the stated deadline – no late work accepted.    

Exams: 3 one-hour exams (see schedule below - subject to change)

Grading: The final grade is based on the grades for the exams and lab projects and reports.

The weight for each part is: Exams 50%, Labs 50%. Grade A (> 90), B (80-90), C (70-80)

Course Syllabus

See course description above


·         Module 1 Introduction

·         Module 2 Verilog for Synthesis – Combinational Logic

·         Module 3 & 4: Verilog – Sequential Logic

·         Module 5: Verilog – Misc topics

·         Module 6: Test benches – Verilog for Testing

·         Module 8: Verilog for Advanced Testing

·         Embedded Processors

·         Memory Interface

·         Verilog for Modeling

·         Metastability, clock domains, pipelines


Lab Assignments

·         Lab exercise 1: (5% of total lab grade)

·         Lab exercise 2:

o   VGA Controller

o   PmodALS data sheet

·         Lab exercise 3

o   PmodDAC data sheet

·         Lab exercise 4 (due Wednesday at noon, October 11th)


Useful Links and Files

·         Xilinx website

·         Xilinx Vivado HL Webpack edition


o   You must first register, and then download and install the WebPack

o   (we just need the Xilinx Vivado Design Suite HL Webpack – logic design edition with SDK. Select SDK during the Webpack customization installation options.)

·         Digilent Website

o   Manufacturer of various FPGA development boards

o   Link to Basys3 board reference material

·         Basys3 Tutorials:

o   Verilog Decoder Tutorial

o   Verilog Counter Tutorial

o   MMCM tutorial (verilog)

o   Simple Simulation (Test Fixture) Tutorial

·         Microblaze Resources:

o   Microblaze Vivado Tutorial to add Microblaze MCS to project (old ISE version)

o   Microblaze MCS Data Sheets

o   PG116 Microblaze Microcontroller Product Guide

o   DS865 Xilinx Product Specification for Microblaze Micro Controller System


·         Older material for reference:

o   Nexys3 (Spartan 6) Board Tutorials:

§  Verilog Decoder Tutorial, VHDL Decoder Tutorial – (for Xilinx synthesis and downloading to the Nexys3 board)

§  DCM Tutorial (Verilog)

§  DCM Tutorial (VHDL)

o   Nexsys2 (Spartan 3E) Board Tutorials (very old for reference):

§  VHDL Counter Tutorial – Verilog Version with Simulation

§  VHDL (with Verilog) Encoder Synthesis and Simulation

§  Xilinx Test Bench Tutorial


·         Picoblaze Resources (just for reference):

o   Xilinx Pixoblaze

§  Select the Picoblaze for the Spartan 3 and download the design files (includes examples)

§  Important: Download and read the UG129 "Picoblaze 8-bit embedded microcontroller" document

o   Mediatronix website

§  Select the pBlazeIDE and download V3.6 of the assembler/simulator

o   Simple Picoblaze example project files for Nexsys2 Board - uses LEDs, DIP switches, and UART

§  ece574_pico.vhd is the top level file, ece574.psm is the assembler file, target is Nexsys2 board.

o   Simple Picoblaze example project files (Verilog Version) for Nexsys2 Board - uses LEDs, DIP switches, and UART

§  ece574_pico.v is the top level file, ece574.psm is the assembler file, target is Nexsys2 board.


·         Paper presented at MSE 2005 on Embedded System Design with FPGAs using HDLs

·         Ten Simple Rules to follow!

·         VHDL FAQ ( – very useful resource

·         Xilinx Zynq-7000 Programmable SoC new device, just for reference

o   ZedBoard



Course Schedule A Term 2017 (subject to change)









Aug 24


Aug 28

Lab 1 signoff


Lab 1 signoff


No class

(Labor Day)




No class

Sep 11

Lab2 signoff


Lab 2 signoff

Exam 1

Lab 2 report

Sep 18





Sep 25

Lab 3 signoff

Lab 3 Signoff

Exam 2 

Lab 3 report

Oct 2





Oct 9

Lab 4 signoff  

Lab 4 report

Exam 3

Academic Honesty:          

Although it is OK to discuss outside of class laboratory projects and exam questions, all work turned in for project assignments and examinations is expected to represent individual solutions to the problems, and laboratory reports are expected to represent the work of the individual or team named on the cover page. Having one person complete an assignment and another person simply duplicating the answers or report is considered a violation of academic honesty. Similarly, duplication of materials such as design, software, flow diagrams, or other documentation between teams, from past projects, or other sources is not acceptable. It is also not acceptable to use ANY VHDL or Verilog code from outside sources (including the Xilinx CORE generator) unless specifically mentioned in the lab description. All VHDL or Verilog must be your own design. Copying another person’s examinations papers, or working from someone else’s notes, or using material in addition to that allowed during an exam, is considered dishonest as well. Any acts of academic dishonesty will, at the least, result in immediate failure of the course for all individuals involved.

Copyright © 2017 R. James Duckworth.

Developed and maintained by R. James Duckworth, .