ECE3829: Advanced Digital System Design with FPGAs

A Term 2020

IMPORTANT: Changes may be required as dictated by Covid-19 requirements.

Preliminary plans are for remote lectures via zoom, and in-person lab sessions.

This is a new course replacing ECE3810. It is recommended for anyone who has taken ECE2029 and ECE2049.

You will need the Digilent BASYS3 development board (you should have this already from ECE2029) to be able to complete the lab assignments. You can buy this board for $89 (academic pricing) directly from Digilent:

http://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/

or from the WPI bookstore.

If you want to work at home on the lab projects (recommended) than you will need to install the Xilinx Vivado Design Suite HL Webpack edition on your own PC (note the OS and system requirements). We just need the logic design version with SDK (select SDK during the Webpack customization installation options).

We will use the Basys3 board and Xilinx software throughout the course for the four lab assignments.

Lecturer.

Dr. R. James Duckworth, AK214, Tel: (508) 831-5204, email: rjduck@wpi.edu

Office hours: send email for zoom meeting

Staff.

Graduate Tutor: Xiao Zhang xzhang25@wpi.edu

Senior Tutor: Jeffrey Collard jicollard@wpi.edu

Lectures, Labs.

25 lectures (remote) including three exams

Lab sessions: (in AK113) Tuesday 8 to 10.50, 2 to 4.50, and Thursday 2 to 4.50

Extra Help/Lab sessions: Saturday and Sunday 2 to 4pm (in AK113)

Note: You only need to go to lab sessions to get help or to have your projects signed off.

Course Description

This course covers the systematic design of advanced digital systems using FPGAs. The emphasis is on top-down design starting with high level models using a hardware description language (such as VHDL or Verilog) as a tool for the design, synthesis, modeling, test bench development, and testing and verification of complete digital systems. These types of systems include the use of embedded soft core processors as well as lower level modules created from custom logic or imported IP blocks. Interfaces will be developed to access devices external to the FPGA such as memory or peripheral communication devices. The integration of tools and design methodologies will be addressed through a discussion of system on a chip (SOC) integration, methodologies, design for performance, and design for test.

Topics: 1. hardware description languages, system modeling, synthesis, simulation and testing of digital circuits; 2. design integration to achieve specific system design goals including architecture, planning and integration, and testing; 3 use of soft core and IP modules to meet specific architecture and design goals.

Laboratory exercises: Students will design and implement a complete sophisticated embedded digital system on an FPGA. HDL design of digital systems including lower level components and integration of higher level IP cores, simulating the design with test benches, and synthesizing and implementing these designs with FPGA development boards including interfacing to external devices.

Recommended background: ECE2029 and ECE 2049

Notes: Students may not receive credit for ECE3829 if they have received credit for ECE 3810.

Textbook: (Not required but recommended) FPGA Prototyping by SystemVerilog Examples: Xilinx MicroBlaze MCS SoC Edition Pong P. Chu, Wiley (ISBN: 978-1-119-28270-9)

An inexpensive ($19.95) reference book is Verilog by Example – A Concise Introduction for FPGA Design, by Readler (ISBN 978-0-9834973-0-1)

Help Sessions: See TA and Senior Tutor help session above

Homework: There is no formal homework for the course but make sure you try lots of design examples and read the reference materials and data sheets.

Lab Assignments: There will be four labs. Lab signoff and reports are expected by the stated deadline – no late work accepted.

Exams: 3 one-hour exams (see schedule below - subject to change)

Grading: The final grade is based on the grades for the exams and lab projects and reports.

The weight for each part is: Exams 50%, Labs 50%. Grade A (> 90), B (80-90), C (70-80)

Course Syllabus

See course description above

Presentations

· Module 1 Introduction

· Module 2 Verilog for Synthesis – Combinational Logic

· Module 3 & 4: Verilog – Sequential Logic

· Module 5: Verilog – Misc topics

· Module 6: Test benches – Verilog for Testing

· Module 8: Verilog for Advanced Testing

· Embedded Processors

· Memory Interface

· Verilog for Modeling

· Metastability, clock domains, pipelines

Lab Assignments - See Canvas for A20 Lab assignments

Useful Links and Files

· Xilinx website

· Xilinx Vivado HL Webpack edition

o http://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html

o You must first register, and then download and install the WebPack

o (we just need the Xilinx Vivado Design Suite HL Webpack – logic design edition with SDK. Select SDK during the Webpack customization installation options.)

· Digilent Website

o Manufacturer of various FPGA development boards

o Link to Basys3 board reference material https://reference.digilentinc.com/basys3:basys3

· Basys3 Tutorials:

o Verilog Decoder Tutorial

o Verilog Counter Tutorial

o MMCM tutorial (verilog)

o Simple Simulation (Test Fixture) Tutorial

· Microblaze Resources:

o Microblaze Vivado Tutorial to add Microblaze MCS to project (old ISE version)

o Microblaze MCS Data Sheets

o PG116 Microblaze Microcontroller Product Guide

o DS865 Xilinx Product Specification for Microblaze Micro Controller System

· Paper presented at MSE 2005 on Embedded System Design with FPGAs using HDLs

· Ten Simple Rules to follow!

· VHDL FAQ (http://www.eda.org/comp.lang.vhdl/) – very useful resource

· Xilinx Zynq-7000 Programmable SoC new device, just for reference

o ZedBoard

Course Schedule A Term 2020 (subject to minor change)

Monday	Tuesday	Wednesday	Thursday	Friday
Aug 31	Lab 1 signoff		Lab 1 signoff
Sep 7 (labor day)
Sep 14	Lab2 signoff		Lab 2 signoff Exam 1	Lab 2 report
Sep 21
Sep 28	Lab 3 signoff		Lab 3 Signoff Exam 2	Lab 3 report
Oct 5
Oct 12	Lab 4 signoff		Lab 4 signoff Exam 3	Lab 4 Report

Academic Honesty:

Although it is OK to discuss outside of class laboratory projects and exam questions, all work turned in for project assignments and examinations is expected to represent individual solutions to the problems, and laboratory reports are expected to represent the work of the individual or team named on the cover page. Having one person complete an assignment and another person simply duplicating the answers or report is considered a violation of academic honesty. Similarly, duplication of materials such as design, software, flow diagrams, or other documentation between teams, from past projects, or other sources is not acceptable. It is also not acceptable to use ANY VHDL or Verilog code from outside sources (including the Xilinx CORE generator) unless specifically mentioned in the lab description. All VHDL or Verilog must be your own design. Copying another person’s examinations papers, or working from someone else’s notes, or using material in addition to that allowed during an exam, is considered dishonest as well. Any acts of academic dishonesty will, at the least, result in immediate failure of the course for all individuals involved.

Developed and maintained by R. James Duckworth, rjduck@wpi.edu .